1. Field of the Invention
The present invention is generally related to multi-chip modules.
2. Problem to be Solved
A multi-chip-module (MCM) is a module or package capable of supporting several chips on a single package. Most multi-chip packages are made of ceramic. Multi-chip-modules offer space and performance advantages over traditional electronic component packaging. MCMs are currently used in applications requiring high performance. As system clock frequencies of personal computers approach 200 MHz and functional densities are increased, more electronic circuit designs will require MCMs. MCMs typically provide cost benefits. However, test and diagnostics issues are two key inhibitors to the widespread adoption of MCM technology. MCMs are difficult to test and are difficult to diagnose when failure occurs.
Test vectors generated for individual chips (in packaged or wafer form) assume that all the necessary chip signal inputs and outputs (I/O) are available to the test equipment. On electronic component packages, it is highly desirable to have as many accessible inputs/outputs (I/Os) as possible. Test engineers typically require as many accessible I/Os as possible to facilitate testing and diagnostic analysis. However, circuit designers want to use the I/Os to enable more functions on the module. When there are too many I/O, the cost of the board to which the electronic component package is connected increases because the wiring becomes complicated and the costs of the socket increases.
Test data used to test chips individually cannot be used to test chips mounted on an MCM. MCM level testing is a relatively higher level of testing than wafer or single-chip-package level testing. Automatic test pattern generation (ATPG) software is typically used in manufacturing processes to generate test data for an individual chip or die. However, such software is typically not configured to generate test data for the logic realized by an MCM due to the MCM's size, i.e. the large number of chips mounted on the MCM.
As developments in semiconductor technology continue, CMOS (complementary metal-oxide semiconductor) in particular, the number of circuits that can be realized on individual chips increase. Thus, it becomes more difficult to generate test data for such high density chips. For multi-chip modules having several chips on one module, the problem is magnified. For example, if there is difficulty in generating tests for a microprocessor chip having about seven (7) million transistors, there will be even greater difficulty trying to generate a unique set of test patterns for a multi-chip module composed of the microprocessor and several other chips having comparable densities. In order to generate test data for the entire module, a separate logic model of the entire MCM must be created before generating the data. Such a separate logic model is significantly more complex than the logic models created to generate test data for individual chips or die. Furthermore, MCM logic models require significantly more computer processing time than generation of test data for individual chips.
Another problem in testing MCMs is the inability to fault-isolate inoperative chips. Some chip I/Os are not accessible when the chips are mounted to an MCM. It is typically desired to characterize critical nets in terms of rise-times, set-up, hold times and other operating parameters when an MCM is initially powered-up. As used herein, the term "nets" refers to a group of terminals interconnected to have a common d.c. electrical potential in an electrical component package. Typically, such critical nets on MCMs cannot be characterized because they do not project from the module and are not accessible. Thus, probes and other detection equipment are of no use when trying to test such nets. Therefore, if a faulty net exists between two or more chips on a multi-chip package, it is difficult to determine the location of the defect. Such difficulty decreases production yield. Furthermore, since fault-isolation to a specific chip is not possible, it is often necessary to replace the entire module if a defective chip exists on the module. This is significantly more expensive than replacing a single defective chip.
An example illustrating the difficulties and problems that exists when it is not possible to fault-isolate to an individual chip is an MCM that has one chip that transmits signals (a driver chip) and another chip receiving the signals (a receiver chip) and the connection between the driver chip and receiver chip is embedded within the MCM substrate and is not accessible. If during testing of the MCM, the receiving chip does not receive the transmitted signals, it must be determined whether the failure is due to: (i) a defective driver chip, (ii) a defective receiver chip, or (iii) a break in the connection between the driver and receiver chips.
It is difficult, if not impossible, to change the design once the first batch of MCM carriers have been fabricated. Altering the MCM substrate layers and assembling the carrier typically consumes significantly more time than making similar changes to a printed circuit board. Furthermore, unlike an MCM, a printed circuit board wiring may be changed by physically drilling new openings and adding solder wires where necessary. Such changes cannot be made to the MCM without damaging or rendering the MCM inoperative.
There have been many attempts to solve the aforementioned problems of testing MCMs. One method involves the addition of pins to the bottom of the module in order to gain access to nets on the module. However, this increases manufacturing costs. Furthermore, the pins are typically gold-plated and therefore expensive. Additionally, these pins would only be used for testing purposes and would not be used as an input or output when the MCM was in operation in its actual environment. The problem then arises of what to do with these pins once testing is complete. One solution is to alter the final circuit board to which the MCM is mounted to provide additional openings to receive the additional pins added to the MCM. Again, this increases manufacturing costs.
Another attempt is to thoroughly test the dies or chips before they are mounted to the module such that the quality and reliability of the module will be high after it is assembled. This is accomplished by testing and burning-in (stressing) the bare dies before they are packaged on the MCM. Although this may appear to solve the test and diagnostic problem by eliminating extensive testing and diagnostic procedures at the module level, this technique normally involves expensive fixturing to handle and contact the die.
Another attempt to solve the aforementioned problems relating to testing MCMs is known as "self-test". Although "self testing" exists in many forms, the basic concept comprises designing logic into a chip such that the chip tests itself with minimal effort with the use of peripheral test equipment. The "self-test" technique reduces the number of pins that need to be contacted by the test equipment. However, the additional logic designed into the chip requires additional engineering, design and manufacturing time thereby significantly increasing the costs to produce the chip.
A further attempt to solve the problems relating to testing MCMs is boundary scan-based testing. Although boundary scan based testing provides controllability and observability with respect to nodes internal to the module that cannot be probed, boundary scanning can actually degrade the performance of the die or chip being tested.
Still, another attempt to solve the problems of testing MCMs is referred to as "chip-in-place" testing. This technique entails contacting EC pads around an individual chip with a gang probe to test that chip while all other chips on the MCM are configured in a tri-state condition, i.e. turned off. After a chip is tested, the gang probe is automatically positioned over the next chip on the module. This process continues until all the chips are tested. This technique is used when there is no free space on the bottom of the module and all test pads on the MCM are on the same side as the chips. However, gang probes are expensive and relatively unreliable. Furthermore, positioning the probe on the pads involves expensive optics and positioning systems.
Bearing in mind the problems and deficiencies of prior systems for testing multi-chip-modules, it is an object of the present invention to provide a multi-chip-module that permits testing of all integrated chips mounted thereto.
It is another object of the present invention to provide a multi-chip-module that allows for testing of all nets embedded in the substrate of the multi-chip-module.
A further object of the invention is to provide a multi-chip-module that allows for testing of all integrated circuit chips mounted thereto in relatively less time than for conventional multi-chip-modules.
It is yet another object of the present invention to provide a multi-chip-module that allows for testing of all integrated circuit chips mounted thereto in a cost effective manner.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.